Rule-based VLSI verification system constrained by layout parasitics
J. Wenin, J. Verhasselt, Marieke Van Camp, J. Leonard, P.P. Guebels · 1989
This paper addresses a rule-based method for VLSI design review, constrained by parasitics. Using the new ideas discussed in this paper, extraction from layout is not limited anymore to conventional electrical data, but additionally allows modelling of functional and timing behaviour. An extendable rule based validation algorithm operates on extracted models, decorated with parasitic effects, to formally prove most aspects of design correctness.