At-Speed Logic BIST for IP Cores
B. Cheon, Eunha Lee, L.-T. Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H.H. Chao, S. Wu · Design, Automation, and Test in Europe · 2005
This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.