A DSP architecture for 64 kbps motion video codec
Tsuyoshi MURAKAMI, Koh Kamizawa, Michitaka Kameyama, S. Nakagawa · 2003
The authors describe an architectural study of a digital signal processor (DSP) well suited for video codec. This DSP consists of specified resources optimized for video signal processing, such as the instruction set, buses, data memories, execution unit, address generators, sequencer, and DMAC. The performance of the DSP is evaluated through several video coding sequences. The architecture of a multiprocessor configuration for video codec, which will allow flexible algorithm and variable picture format, is also examined.>