Reliability analysis techniques for complex multiple fault tolerant computer architectures
Arun K. Somani, T.R. Sarnaik · IEEE Transactions on Reliability · 1990
Several issues on reliability analysis of complex multiple-fault-tolerant computer systems are addressed, and techniques are developed to reduce the complexity of the reliability model. Two-fault-tolerant architectural concepts (the matrix-voter-based architecture, MVA, and the channel-voter-based architecture, CVA) developed for a computer node in a distributed embedded environment are used as examples. These two architectures are analyzed including the dynamics of transient and intermittent faults. The relationship between the number of retries and its effect upon system reliability has been analyzed for various average transient lifetimes. The MVA, although structurally regular, is more challenging for reliability analysis than the CVA. The system unreliability decreases as the reliability of the MVA is rather insensitive to the bus-interface unit failures. For the same parameter values, the MVA has an unreliability 1/10 that of the CVA.>