Emulative testing at the bus speed limit
Dave Arnett, KasiS Bhaskar · 2003
An alternative is attempted to the bus-switch for bus cycle emulation, preferably one that was programmable, so as to minimize the amount of hardware to be designed for each microprocessor to be emulated. The evolution of the hardware architecture from the basic concept is discussed first, followed by a discussion of issues involved in programming the emulation. A problem-solution format is used to present each topic; problems that arise are described, and then proposed solutions are explained.>