A neuron processor for neural networks on silicon
J. Ouali, G. Saucier · 2002
A neuron processor has been designed and implemented on silicon in a 1.5 mu m CMOS technology. It implements a relaxation algorithm with 8 bits precision for the state and the coefficients, and a sigmoidal activation function. It is the building block of a distributed synchronous architecture in which data circulate through shifting techniques.>