MediaSoC: a system-on-chip architecture for multimedia application
Peng Liu, Weidong Wang, Zhibin Xiao, Li-ya Lai, Zhao-wei Teng, Guojun Yu, Yingbiao Yao, Keming Chen, Zhidi Jiang, Yixiong Zhang, Jian Zhou, Wang Ca, Zhi-bo Zhai Ce Shi, Qingdong Yao · 2005
The MediaSoC322IA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with tie processor cores. The MediaSoC3221A is fabricated in a 0.18/spl mu/m 6LM standard-cell SMIC CMOS technology, occupies about 20 mm/sup 2/, and operates at 180 MHz. The MeidaSoC3221A are used to audio/video decoder for embedded multimedia application.