Timing issues related to the automated placement and routing of high performance ASICs
M. Swinnen, Guido Arnout · 2002
Discusses the timing issues and methodologies involved in the automated placement and routing of high speed ASICs. As device sizes shrink and clock speeds increase, timing driven layout becomes critical in meeting time-to-market deadlines. The concepts covered include clock tree synthesis, net timing constraints, critical path timing constraints, pin-to-pin delay calculation and back-annotation.>