Low-power DV encoder architecture for digital CMOS camcorder
J.Y.F. Hsieh, T.H. Meng · 1999
A low-power, large-scale parallel digital video (DV) [1] encoder architecture for a single-chip digital CMOS video camera is discussed in this paper. This architecture is based on the single chip CMOS camera MPEG-2 encoder architecture proposed in [2] with an emphasis on formatting and streaming of the compressed data. The architecture proposed here supports the 625/25 format of 720/spl times/576 pixels per frame. When clocked at 40 MHz, this architecture delivers a processing performance of 1.8 billion operations per second (BOPS) capable of supporting a frame rate of 25 fps as well as additional image enhancement processing. Low power consumption is achieved by the use of a parallel architecture and low-power circuit design techniques. When implemented in a 0.2 micron CMOS technology at a 1.5 V supply voltage, the parallel architecture consumes 45 mW providing a power efficiency of 40 billion operations per second per Watt.