Adder and comparator synthesis with exclusive-OR transform of inputs
Josia Jacob, P. Sivakumar, V.D. Agrawal · 2002
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n/sup 2/). In comparison, when the complete truth-table of an adder is minimized, the PLA size will be O(2/sup n+2/). Similarly, for an n bit comparator, the size of the PLA is reduced from O(2/sup n+1/) to O(n). These implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates.