A chip for realtime skeleting of images
Reinhard Rauscher, A.J. Maeder · 2002
A chip performing the special task of thinning (a common task in the field of image processing) is presented. The most important design decisions, the results, the layout, and the aspects of testability are described. The chip will be fabricated in a 2 mu m-CMOS process in standard-cell technique, using the VENUS system from the Siemens Company. It has 45 pins in all, measures 38.6 mm/sup 2/, and contains about 32000 transistors. About 24200 are included into 3 on-chip RAMs, and 3500 are used to implement the deletion procedure itself, realized as a combinational circuit. A discrete prototype (containing about 100 ICs) of the overall design has been designed. In comparison to a software solution based on a transputer environment, a decrease of calculation time of factor 100 is determined.>