FPGA implementation of low latency routing algorithm for 3D Network on Chip
A. Vino Vilmet Rose, R. Seshasayanan, G. Oviya · 2011
Network on chip (NoC) is the most promising on-chip communication architecture. The three dimensional integration of NoC is achieved by stacking 2D layers. The communication between the layers is achieved by the presence of vertical links between the 3D nodes. We propose a deterministic routing scheme for choosing the 3D node and it uses the xy routing within the 2D layers. Our algorithm finds path from any source to specified destination. The unique feature of this model is the search for the proximal vertical 3D node towards the destination router. It is inferred from the result that the routing scheme can achieve better performance in terms of reduced latency compared with the 3D routing method. The algorithm is implemented in FPGA.