An efficient hardwired router for a 3D-mesh interconnection network
Jean-Luc Béchennec, Cécile Germain, Vincent Néri · 2002
A routing circuit for massively parallel message-passing architectures is presented. This circuit meets the area requirements of a monochip processing element and is time-efficient. It implements a new routing algorithm, forced routing. It is shown that the forced routing algorithm may be hardwired in less than a 10 mm/sup 2/ circuit in a CMOS 1.2 mu m process. Several design choices are discussed and tested for the arbiter, which is the most critical part of the circuit.>