An embedded technique for at-speed interconnect testing
Benoit Nadeau-Dostie, J-F Cote, H. Hulvershorn, S. Pateras · 2003
A new embedded test technique which provides full at-speed testing of board level interconnect is described. The proposed technique is fully compatible with the IEEE 1149.1 boundary scan standard. The technique extends the standard's architecture to provide for synchronized at-speed timing control of the boundary scan cells so that test data can be applied and captured across the interconnect at system speeds.