An asynchronous synthesis toolset using Verilog
Frank Burns, Delong Shang, Albert Koelmans, Alex Yakovlev · 2004
We present a new CAD tool set for generating asyn-chronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits us-ing David Cells (DCs). Finally logic optimization tools are applied to generate speed independent (SI) circuits. The speed independent circuits generated perform well com-pared to circuits generated by existing asynchronous tools. 1.