CMOS overcurrent test: BIC-monitor design, circuit partitioning and test patterns
H.T. Vierhaus, L. Muhlack, Uwe Glaser · 2002
The successful implementation of built-in current monitoring circuitry is the key to the practical applicability of defect-oriented CMOS test via current effects. However, inherent constraints due to dynamic effects and the overhead for large chips are still open problems. This paper introduces a novel current monitor design, provides guidelines for circuit partitioning into current-monitor blocks and gives realistic numbers of test patterns for current-versus voltage test.>