Bounding DMA Interference on Hard-Real-Time Embedded Systems *
Taiyi Huang, Chih-Chieh Chou, Po‐Yuan Chen · 2006
A DMA controller that operates in the cycle-stealing mode transfers data by stealing bus cycles from the CPU. The concurrent contention for the I/O bus by a CPU task and a cycle-stealing DMA I/O task retards their progress and extends their execution times. In this paper we first describe a method for bounding the worst-case execution time (WCET) of a CPU task when cycle-stealing DMA I/O is present. We next use the dynamic-programming technique to develop a method for bounding the WCET of a cycle-stealing DMA I/O task executing concurrently with a set of CPU tasks. We conducted exhaustive simulations on a widely-used embedded processor. The experimental results demonstrate that our methods tightly bound the WCETs of CPU tasks and of cycle-stealing DMA I/O tasks. Keywords: hard-real-time systems, worst-case execution time, cycle-stealing DMA I/O, concurrent execution, embedded systems 1.