A HW/SW Co-design Tool for Modern FPGA's with FPGA-Embedded Processors
Jason Scott, Ted Bapty, Sandeep K. Neema, Brandon Eames, Andrew Vandivort, Sarir Khamsi, Troy Gangwer · 2004
Field Programmable Gate-Arrays (FPGA) containing one or more embedded processor cores within the FPGA fabric (both hard & soft processor cores) are quickly becoming a mainstream architecture for highperformance signal processing. Design tools for these new architectures from FPGA vendors have steadily matured to provide a viable, if laborious, solution for designers. These tools merge software compilers, hardware compilers, and basic IP to support a manual SOC design process. Given the complexity of potential target systems, there is a need to design at a higher level. The current FPGA-plus-embedded processor core combination provides great opportunity for highperformance systems. The strengths of both the FPGA fabric to implement highly optimized hardware processing functions and a processor core to provide overall control and flexible processing tasks not suited for hardware implementation. In designing these systems, it is critical that bottlenecks in the control flow do not impact the time-critical data flow of the application. This paper describes the ongoing work in developing a high-level co-design design environment for the latest FPGA SOC architectures.