A median filter FPGA with Harvard Architecture
Junxia Zhao, Zhen Botao, Hongjun Liu · International Conference on Information Science and Technology · 2011
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part of the multi-image processing chip.