Design techniques for HDTV switched-current decimators
M. Helfenstein, J.E. Franca, G.S. Moschytz · 2002
The design of switched-current decimators for wide bandwidth video filtering applications is presented. Applying topologies with only one input commutator to switched-currents allows the design of high speed polyphase input branches with reduced distortion. These concepts were utilized in the implementation of a linear phase 19 tap FIR filter chip with an amplitude response tailored to video applications. It is expected that the prototype filter implemented in a 0.5 /spl mu/m CMOS process will operate at an input sampling rate of 135 MHz and with a decimating factor of 5.