A multi level testability assistant for VLSI design
Massimo Bombana, G. Buonanno, P. Cavalloro, Donatella Sciuto, G. Zaza · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 1992
The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules. >