Test set embedding in a built-in self-test environment
Sheldon B. Akers, W. Jansz · 2003
The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates. A precomputed set of tests (obtained through some test generation scheme) is required for this approach. A subset of this set of tests forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques. Simulation of this BIST technique on various benchmark circuits has given good results in terms of both coverage and hardware size.>