Verilog simulation of Xilinx designs
Clifford E. Cummings · 2002
Details design flows to capture Xilinx designs and translate them into Verilog behavioral models. Part of this material focuses on back annotation of Xilinx routed timing information into a Verilog simulation. The author also describes modified design flows to take advantage of third-party FPGA design tools and mixing of Xilinx design methodologies.>