On the implementation of shifters, multipliers, and dividers in VLSI floating point units
Victor Peng, Sridhar Samudrala, Moshe Gavrielov · 1987
Several options for the implementation of combinatorial shifters, multipliers, and dividers for a VLSI floating point unit are presented and compared. The comparisons are made in the context of a single chip implementation in light of the constraints imposed by currently available MOS technology.