Implementation of an 8000 BPS CELP coder on a single TMS320C25 digital signal processor chip
K. Bryden, A. Brind'Amour, H. Hassanein · 2003
The implementation of a code-excited linear-predictive coder on a single TMS320C25 digital signal processor is described. In this implementation, an excitation vector selected from a 32-entry waveform codebook drives a cascade of a single coefficient lag synthesis filter followed by a ten-coefficient format synthesis filter to produce good-quality speech at 8000 b/s.>