Partial run-time reconfiguration of FPGA for computer vision applications
Manish Birla, Karimella Vikram · Proceedings - IEEE International Parallel and Distributed Processing Symposium · 2008
FPGAs are a popular platform for implementation of computer vision applications, due to the inherent parallelism present in the programmable fabric. In addition to hardware acceleration through parallelization, modern FPGAs are also dynamically reconfigurable, thereby adding an additional dimension to the mapping of algorithms to hardware. Among the various uses for run-time reconfiguration, one application is the time multiplexing of limited hardware resources to carry out a considerably complex computation. This paper presents the use of partial reconfiguration for time multiplexing computations in the implementation of a computer vision application - human detection. The results obtained from the implementation of a proof-of-concept prototype on a Xilinx Virtex-4 FPGA are also presented.