Memory hierarchy design for a multiprocessor look-up engine
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney · 2003
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the number of and contention for memory accesses. Using a level compressed trie as an index, we show the impact of the main parameter, the root branching factor, on the memory capacity and number of memory accesses. Despite the lack of locality, we show how a cache can re-duce the required memory capacity and limit the amount of expensive multibanking. Results of simulation experiments using contemporary routing tables show that the architec-ture scales well, at least up to 16 processors, and that the presence of a small on-chip cache increases throughput sig-nificantly, up to 65 % over an architecture with the same number of processors but without a cache, all while reduc-ing the amount of required off-chip memory. 1