Recovery Mechanism for Latency Misprediction
Enric Morancho, José María Llabería, Àngel Olivé · 2001
In dynamically-scheduled superscalar processors, instruc-tions wait in the issue queue for the availability of operands and functional units [8][13][16][17]. To issue instructionsout-of-order to the functional units, the issue queue has two components: a) wakeup logic and b) select logic. The wakeuplogic keeps monitoring the dependencies among the instructions in the issue queue and, when the operands of a queuedinstruction become available, this logic will mark the instruction as ready. The select logic selects which instructions willbe issued to the functional units on the next cycle.