An ATPG driver selection algorithm for interconnect test with boundary scan
Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-ziq · 1992
In a board level design with boundary scan, an interconnect is testable if it can be controlled and observed through the scan chain(s). One or more activated drivers can drive a net to the desired logic state, and the receiver(s) can observe the state of that net. To select driver(s) and receiver(s) for a testable net, associated control cell(s) has to be programmed with proper value(s). A conflict arises when a control cell value programmed for one net is different from the value previously programmed for another net. A driver selection algorithm is presented here to resolve such a conflict.