Architecture of an Efficient Area and Flexible Multi-CODEC Processor
Ji Hwan Park, Hee Ju Park, Jeong Hun Kim, Kyusam Lim, Suki Kim · 2006
In this paper, an architecture of a multi-CODEC processor is presented as a solution to have an efficient area and flexibility. In order to acquire cost efficiency, flexibility and high performance in terms of architecture, three techniques are applied. The first is SIMD architecture, the second is pipelining and the last is double buffering. The performance of the designed core is increased to adopt CIF in real-time constraint. A chip area of the proposed processor is reduced more than conventional method which is implemented to each block in various CODEC. Finally, total gate count is 66.5 K and memory size is 1.7 KB in magna-chips 0.25 mum technology.