Design of a second-level cache chip for shared-bus multimicroprocessor systems
Kota Uchiyama, Hirokazu Aoki, Osamu Nishii, S. Hatano, O. Nagashima, Kanji Oishi, J. Kitano · IEEE Journal of Solid-State Circuits · 1991
The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic.>