A VLSI implementation of multi-layer neural network with ternary activation functions and limited integer weights
B.G. Hoskins, Malcolm R. Haskard, G.R. Curkowicz · 2002
This paper describes a digital neural network architecture and its VLSI implementation. Multi-layer neural networks are made feasible through input and output signal multiplexing, ternary quantisation of signals and integer weights. Use of the chip is demonstrated in the simulation of a character recognition problem.