Area-Efficient NEDA Architecture for The 1-D DCT/IDCT
Archana Chidanandan, Magdy Bayoumi · 2006
A new distributed arithmetic has been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper, we apply NEDA to the even-odd decomposition matrices of the 8times8 forward and inverse DCT. We show that, with the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8times8 DCT and IDCT matrices. This reduction results in power savings, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding