Post Synthesis Level Power Modeling of FPGAs
Matthew French, Li Wang, Timothy H. Anderson, Michael Wirthlin · 2005
In this paper we outline a methodology and tool suite capable of modeling the power consumption of an FPGA design at the post synthesis, or EDIF, level. Modeling at this level has the following advantages: 1) early power feedback in the design flow, 2) power results displayed at a high level, closer to the logical design entry point 3) and the elimination of bulky, low-level timing accurate simulation and stimulus files. These three aspects allow a designer to quickly and easily generate power estimates, relate the results back to their original logical level design entry, and explore design trade-off scenarios. The results presented here were derived using Xilinx Virtex2 FPGAs and tool suites, however the techniques apply to all FPGAs.