A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division
F. Monteiro, A. Dandache, A. M'sir, B. Lepley · 2002
The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits).