A digit-serial architecture for inversion and multiplication in GF(2M)
Junfeng Fan, Ingrid M.R. Verbauwhede · 2008
Modular multiplication and inversion are the essential operations in many Public Key Cryptosystems (PKCs). In this paper, we describe a unified digit-serial inverter/multiplier in GF(2m). The inversion is based on a modified Extended Euclidean Algorithm (EEA), while the multiplication is based a LSB-first multiplication algorithm. As the inverter and multiplier share the data-path, it is smaller than Arithmetic Logic Units (ALUs) with separated inverters and multipliers. When choosing digit size to be w, this inverter/multiplier finishes one inversion and one multiplication in [2m−1/w] and [m/w]clock cycles, respectively.