A high speed data encryption processor for public key cryptography
T. Rosati · 1989
A cost-effective public key cryptographic architecture and its implementation in 2-μm double-level-metal CMOS are presented. The latter consists of a 593-bit arithmetic processing element, an 8-bit microcontroller, and an intelligent bus interface unit. The device uses 95000 transistors, has an area of 115000 mil2assembled in a 40-pin package, and is capable of an average throughput of 500 kb/s