Synthesis of zero input limit cycle free networks
Jacques Szczupak, Chunyun Sheng · 1991
A method to synthesize digital filter structures free from zero-input limit-cycles is presented, based on the use of structurally bounded real realizations. A time-varying model is used for the network, allowing the analysis of zero-input granularity and overflow oscillations. Simple extensions to forced overflow situations are discussed. The method is illustrated for lower order networks.>