A low-power motion estimation block for low bit-rate wireless video
Rhys Richmond, Dong Sam Ha · 2002
Presents a low-power design of a motion estimation block targeting a low-bit rate video codec H.263. The block is based on the four-step search algorithm. The proposed design offers up to 38% power reduction for logic blocks alone over a "baseline" implementation of the four-step search (4SS) algorithm and up to 58% power reduction over a baseline model of the three-step search (TSS) algorithm. In addition, our design reduces power dissipation of an on-chip memory by up to 32% over the 4SS and 27% over the TSS.