System-level Built-In Self-Test of global routing resources in Virtex-4 FPGAs
Jia Yao, Bobby Dixon, Charles E. Stroud, Victor P. Nelson · 2009
We describe the implementation of a cross-coupled parity built-in self-test (BIST) approach for the global routing resources in field programmable gate arrays (FPGAs). The BIST approach facilitates system-level testing of the FPGA global routing resources prior to configuring the intended system function for high reliability/availability systems. We discuss the application of the BIST approach to the global routing resources in Xilinx Virtex-4 FPGAs including experimental results of implementations in actual devices.