A floating-point vector signal processor (ZSP-325) with concurrent architectures
A. Genusov, P. Feldman, R. Friedlander, V. Fruchter, R. Jaliff, A. Mohr · 2003
A single-chip computation engine for high-throughput, wide-dynamic-range, high-precision digital signal processing (DSP) applications was developed. The processor supports IEEE standard floating-point arithmetic and directly implements vector/matrix DSP primitives. Its concurrent architecture is tuned for operations on multidimensional complex data. The device, fabricated in 1.5- mu m double-level metal CMOS process, contains 115000 transistors on an area of 8.2*10.8 mm/sup 2/ and dissipates 700 mW. A complex 1024-point FFT (fast Fourier transform) is executed in 1.7 ms with a peak performance of 37.5 MFLOPS (million floating-point operations per second) at an external clock frequency of 25 MHz. The compactness and efficiency of the high-level DSP instruction set are discussed in relation to some demanding applications, such as a Kalman filter.>