A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation
Jun Chen, Tadashi Shibata · IEEE Transactions on Circuits and Systems I Regular Papers · 2009
An analog circuit for implementing pulse-coupled neural networks (PCNNs) in very-large-scale integration (VLSI) hardware has been developed using the Neuron-MOS$( u {\rm MOS})$technology. PCNNs are biologically inspired models having powerful ability for image feature generation. With the$ u {\rm MOS}$technology, weighted sum of multiple input signals, which is an essential of PCNNs, is implemented simply by the capacitive coupling effect in a$ u {\rm MOS}$block. By employing the switched floating gates in the$ u {\rm MOS}$blocks as temporary analog memories, the storage of image data is simply realized. Moreover, the function of decay generation, which is crucial for emulating PCNNs neuronal dynamics, is also merged into a$ u {\rm MOS}$block by utilizing the input-terminal capacitors in it. With such techniques, the circuit achieves a purely voltage-mode implementation of PCNNs in a compact structure. Inheriting the merits of PCNNs, the circuit has good discriminability against different patterns as well as robustness against rotation and translation of identical patterns, which is analogous to human image perception. The performance of the circuit has been verified by the measurements of a proof-of-concept chip fabricated in a 0.35-$\mu{\hbox {m}}$double-polysilicon CMOS technology.