Testing of a 32-bit High Performance Embedded Microprocessor
Wang Jing, Zhang Shengbing, Zhang Meng · 2007
This paper describes the testable design and fault coverage analysis for a 32-bit high performance embedded microprocessor which is compatible with PowerPC750 ISA. In the test structure, the TAP controller do on-chip standard boundary scan test, full scan test for core logic and MBIST test for embedded memories. In full scan test, all scan registers are organized to 32 scan chains, the area overhead is less than 3%, the critical path is less than 4ns and meets timing requirement. The fault coverage analysis and chip test result demonstrate that the test strategy and test structure are effective for our embedded processor.