Two-prime RSA immune cryptosystem and its FPGA implementation
Y. Yang, Z. Abid, Wenjia Wang · 2005
In this paper, an efficient immunity method is proposed for two-prime RSA cryptosystem against hardware fault attack. The proposed system has more immunity than the previous system and is targeted for FPGA implementation. For the 32-bit signing case, the proposed method is 15% faster than the previous design while requiring only 70% of the hardware resource.