System-level design verification in the AT&T Computer Division: tools
M. Abramovici, James J. Kulikowski, D.T. Miller, Prem R. Menon · 2003
The authors present the CAD tools used for system-level design verification (DV) in the AT&T computer division. They discuss features of the tools for building and preparing the model of the system, developing tests, simulation, static timing analysis, results analysis, and circuit comparison. While a good simulator is an essential component, many other tools are required. Although some of them provide only relatively minor capabilities, together they form an integrated set of tools that greatly simplify the designers' work and make possible successful completion of system-level DV projects.>