A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications
Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan · 2005
A low-power dynamic reconfigurable FFT fabric is proposed in this paper. The architecture is served as a scalable IP core, which is suitable for system on chip applications. The system can be configured as 16, 32, 64, 128, 256, 512 and 1024-point FFT. Compared with a conventional ASIC FFT processor, this FFT fabric is characterized by having dynamic reconfigurability while incurring only a 12 /spl sim/ 19% increase in energy consumption, and requiring 14% more area than a 1024-point non-reconfigurable FFT fabric. On the other hand, compared with a FFT processor which is mapped onto a general purpose reconfigurable architecture, it has 30 /spl sim/ 94% less energy consumption.