Instruction scheduling for power reduction in processor-based system design
Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura · 1998
Abstract | This paper propose an instruction scheduling technique to reduce power consumed for o-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formu-lated and a scheduling algorithm is also presented. Experimental results demonstrate the eectiveness and the eciency of the proposed algorithm. 1