Modeling and verification of embedded systems using Cadence SMV
A.A. Mir, S. Balakrishnan, Sofiène Tahar · 2002
Embedded systems are becoming increasingly popular due to their widespread applications. For safety-critical applications an approach is needed to validate the complexity of VLSI designs at a higher abstraction level. With formal verification we verify that every possible behavior of the target system satisfies the specification. SMV is a formal verification system for hardware designs, based on a technique called "symbolic model checking". In this paper we investigate the modeling and verification of an embedded system using Cadence SMV. We constructed a Verilog model of the system by integrating the microcontroller RT level and the embedded software assembly code level. We then validate our models and verification by conducting model checking which analyzes essential aspects of the target embedded system.