A Study in Functional Verification of ASIP
Jian Zhou Xu, Jin Hai Su, Zi Bin Dai, Wei Li · Advanced materials research · 2012
ASIP can fulfill data processing effectively and flexibly in specific application. Due to the instruction’s diversity and the flexibility of logical structure, it has increased test vectors and enhanced difficulty in the functional verification of ASIP [1].With the continuous spread of ASIP application, the scale of designing is enlarging and the functional verification has become the bottleneck of designing of ASIP. This paper presents a methodology able to accomplish the functional verification of ASIP. The “Bottom-up” methodology is composed of the component-level verification, the instruction-level verification and the FPGA-based prototype system verification. The paper proves the feasibility and efficiency through the experiments in functional verification of ASIP.