Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo · 2007
In this paper we present an FPGA partition architecture, a methodology and a set of supporting tools that enable the use of partial reconfiguration in two directions: the (re)allocation of tasks within a slot based FPGA arrangement, and the reconfiguration of the communication infrastructure between these tasks and with an external processor. Thus, embedded reconfigurable devices can operate autonomously to adapt themselves when they receive a new task or group of tasks, optimizing both task allocation and intra-task communications. The type of communication structures supported can be a combination of buses, point-to point connections and networks-on-chip (NoC), each with variable width, sharing a fixed set of intra-task communication channels. Results are shown for a remote reconfiguration application, and additional experiments for reconfigurable NoCs are also shown.